gicv2: enable configuring IRQ trigger type

This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.

Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>

diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 7cf6c76e3a604620a0962267400ca2702ab6b62f..a355659d248bf9abea6a15c3170f5098e63b5862 100644 (file)
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -593,3 +593,12 @@ unsigned int gicv2_set_pmr(unsigned int mask)
 
        return old_mask;
 }
+
+/*******************************************************************************
+ * This function updates single interrupt configuration to be level/edge
+ * triggered
+ ******************************************************************************/
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg)
+{
+       gicd_set_icfgr(driver_data->gicd_base, id, cfg);
+}

diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index 925d1c25c19bca2709c1001a6abb11eb5b8d5e14..3472c37d7b49e17e49cfe82260bc90dcfe2a60e6 100644 (file)
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -191,6 +191,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num);
 void gicv2_set_interrupt_pending(unsigned int id);
 void gicv2_clear_interrupt_pending(unsigned int id);
 unsigned int gicv2_set_pmr(unsigned int mask);
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __GICV2_H__ */